EDA技术与应用课后习题答案
WHEN st4=> ALE0<='0';START0<='0';LOCK<='1';OE0<='1';next_state<=st0;
WHEN OTHERS=>next_state<=st0;
END CASE;
IF CLK'EVENT AND CLK= '1' THEN
ALE<=ALE0;START<=START0;LOCK0<=LOCK;OE<=OE0;--方法1:信号锁存后输出
END IF;
END PROCESS COM;
REG:PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1') THEN current_state<=next_state; END IF;
END PROCESS REG; --由信号current_state将当前状态值带出此进程：REG
LATCH1: PROCESS(LOCK) --此进程中，在LOCK的上升沿，将转换好的数据锁入
BEGIN
IF LOCK='1' AND LOCK'EVENT THEN REGL<=D; END IF;
END PROCESS LATCH1;
END behav;
-- 解："【例8-2】根据图8-6状态图，采用Moore型状态机，设计ADC0809采样控制器" 方法2(使用状态码直接输出型状态机)的VHDL程序代码(【例8-7】的根据状态编码表8-1给出ADC0809数据采样的状态机)如下：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY AD0809 IS
PORT( D: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLK,EOC: IN STD_LOGIC;
ALE,START,OE,ADDA:OUT STD_LOGIC;
c_state:OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END AD0809;
ARCHITECTURE behav OF AD0809 IS
SIGNAL current_state,next_state: STD_LOGIC_VECTOR(4 DOWNTO 0);
CONSTANT st0: STD_LOGIC_VECTOR(4 DOWNTO 0):="00000";
CONSTANT st1: STD_LOGIC_VECTOR(4 DOWNTO 0):="11000";
CONSTANT st2: STD_LOGIC_VECTOR(4 DOWNTO 0):="00001";
CONSTANT st3: STD_LOGIC_VECTOR(4 DOWNTO 0):="00100";
CONSTANT st4: STD_LOGIC_VECTOR(4 DOWNTO 0):="00110";
SIGNAL REGL: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL LOCK: STD_LOGIC;
BEGIN
ADDA<='1';Q<=REGL;START<=current_state(4);ALE<=current_state(3);
OE<=current_state(2);LOCK<=current_state(1);c_state<=current_state;
COM: PROCESS(current_state,EOC) BEGIN --规定各状态转换方式
CASE current_state IS
WHEN st0=> next_state<=st1; --0809初始化
WHEN st1=> next_state<=st2; --启动采样
WHEN st2=> IF(EOC='1') THEN next_state<=st3; --EOC=1表明转换结束
ELSE next_state<=st2; --转换未结束，继续等待
END IF;
WHEN st3=> next_state<=st4; --开启OE，输出转换好的数据
WHEN st4=> next_state<=st0;
WHEN OTHERS=> next_state<=st0;
END CASE;
END PROCESS COM;
REG: PROCESS(CLK)
BEGIN
IF (CLK'EVENT AND CLK='1') THEN current_state<=next_state;
END IF;
END PROCESS REG; --由信号current_state将当前状态值带出此进程：REG
LATCH1: PROCESS(LOCK)--此进程中，在LOCK的上升沿，将转换好的数据锁入
BEGIN
IF LOCK='1' AND LOCK'EVENT THEN REGL<=D;
END IF;
END PROCESS LATCH1;
END behav;
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